1. Field of the Invention
The present invention relates to a semiconductor nonvolatile memory and, more particularly, to an erasing operation where overerasing can be prevented.
2. Description of the Related Art
Nowadays, electrically erasable programmable read only memory (E.sup.2 PROM) of a flash type (flash memory hereafter) is know as memory where data is able to be rewritten by using electricity. FIG. 1 shows a memory cell 50 of the flash memory in section. The memory cell 50 comprises a substrate having a well 2 in the surface of which an n+ type source 4 and an n+ type drain 3. On the surface of the well 2 is formed a layer 108 of silicon dioxide. On the silicon oxide layer 108, are formed a floating gate 112 of conductive material underlying a layer 113 of silicon dioxide. A control gate electrode 114 is attached to the layer 113. Note that the thickness of the silicon oxide layer 108 is arranged to be 10 nm.
An operation for writing and erasing data into and from the memory cell will be described. To write a logic "1" into the memory cell, a high voltage of about 12 volts is applied to the control gate electrode 114, a voltage of 7 volts is applied to the drain 3 and ground potential is applied to the source 4. At that time, some carriers of hot electrons generated around the drain 3 tunnel the barrier silicon oxide layer 108 and enter into the floating gate 112.
This changes the potential of the floating gate 112 and thereby increases the threshold voltage (TH) of the memory cell 50 into the threshold voltage Vthh. This state means the memory cell 50 is in the logic "1" state.
Meanwhile, to write a logic "0" into the memory cell 50 or to erase the memory cell 50, the charge carriers previously accumulated in the floating gate 112 are injected through the silicon oxide layer 108 into the source 4 by Fowler-Nordheim tunneling. Specifically, a voltage of -12 volts is applied to the floating gate 112 relative to the source 4 in order to generate an electric field of the opposite polarity to that used when writing the logic "".
This changes the potential of the floating gate 112 and thereby decreases the threshold voltage (TH) of the memory cell 50 into the threshold voltage VthL. This state means the memory cell 50 is in the logic "0" state.
As is described above, the memory cell 50 has two threshold voltages (Vthh in the logic "1" state and VthL in the logic "0" state) of different values.
An operation of reading data from the flash memory cell will be described below. In a reading operation, a voltage Vs of "sense voltage" is applied to the control gate electrode 114. Note that "Sense voltage" is a voltage which is between the threshold voltage Vthh and the threshold voltage VthL.
Specifically, since the "sense voltage" Vs is smaller than the threshold voltage Vthh of the flash memory cell 50 with the logic "1" the channel region 116 remains nonconductive. Therefore, no current flows through the channel region 116 when a bias is applied between the source 4 and the drain 3.
Meanwhile, as the "sense voltage" Vs is larger than the threshold voltage VthL of the flash memory cell 50 in logic "0" the channel region 116 changes from nonconductive into conductive. Therefore, a current flows through the channel region 116 when a bias is applied between the source 4 and the drain 3.
As is described above, it can be determined whether the memory cell 50 is in the logic "1" state or the logic "0" state, by determining whether or not a current flows between the drain 3 and the source 4 using the sense voltage Vs applied to the control gate electrode 114.
Meanwhile, as is described above, the erasing operation is effected by injecting charge carriers from the floating gate 112 into the source 4 by Fowler-Nordheim tunneling.
Note that if the time for erasing the memory cell is not controlled, the threshold voltage TH of the memory cell may decrease into the threshold voltage of 0 volt or less becoming what is referred to as "over erased". The flash memory in an "over erasure" state acts as a depletion mode transistor.
When the memory cells are of "over erased" in a flash memory circuit arrayed in rows and columns, the following problem may occur in a reading operation.
FIG. 3 shows a flash memory circuit constructed by using the memory cell 50 in a partial equivalent circuit.
A reading operation will be described below. Specifically, data is read from a flash memory cell C11, which is effected by applying a sense voltage of 3 volts to the word line WL1n, a voltage of 0 volts to the source line SL, a voltage of 2 volts to the bit line BLn connecting with the flash memory cell C11 and connecting a sense amplifier to the bit line BLn.
Since the channel region 116 is nonconductive when the flash memory cell C11 is in the logic "1" state no current flows between the source 4 and the drain 3. Conversely, since the channel region 116 is conductive when the flash memory cell C11 is in the logic "0" state a current flows between the source 4 and the drain 3. The sense amplifier can detect whether a current flows through the bit line BLn.
Assume that the flash memory cell C13 is in an "over erased" state wherein the cell C13 has the threshold voltage VthL of less than 0 volts. Then, since a voltage of 0 volts is applied to the word line WL2n the channel region 116 of the flash memory cell C13 is conductive. Therefore, a current flows through the channel region 116 of the memory cell C13.
There is an extent of charges injected by F-N tunneling because of errors in the coupling rate and the insulating silicon oxide layer 108 due to an extent of the thickness, surface dimensions and positioning. This extent of charges by F-N tunneling make a flash memory cell "over erased".
Specifically, there is a case where the threshold voltage of a flash memory cell decreases into the threshold voltage VthL and at that time the other flash memory cells have a threshold voltage whose magnitude is larger than the threshold voltage VthL. In this case, in order to erase all the flash memory cells, the time to erase the flash memory cell having the slowest erasing speed is necessary because the erasing speed is different in each flash memory cell. Therefore, the threshold voltage of the flash memory cell having the fastest erasing speed decreases into less than the threshold voltage VthL. That means this memory cell will become "over erased".
To prevent "over erased" due to time for erasing, an internal erase verify reference circuit is used. According to an erase algorithm of the erase verify reference circuit, at first, a writing operation is accomplished to increase the threshold voltages of all memory cells into a certain value. The erase verify reference circuit accomplishes an erasing operation of so short a time as not to overerase cells and verifies that the threshold voltage of memory cells is not more than the threshold voltage VthL. The erase algorithm is designed so that if some cells require more time to reach the erased state, the erase and verify sequence will be iterated until all bytes in the array are less than or equal to the threshold voltage VthL.
Meanwhile, it is known that ruggedness between the floating gate 112 and the substrate brings an extent of the charge by F-N tunneling. There is a method for decreasing the extent of charge by F-N tunneling. The more the concentration of phosphorus in the floating gate 112 increases, the more ruggedness between the floating gate 112 and the substrate occurs. Therefore, the extent of charge by F-N tunneling can be decreased by lowering the concentration of phosphorus in the floating gate 112.
Meanwhile, there is a method for preventing "over erased" using hot hole after erase is accomplished in the above-described normal manner. Specifically, after a cell is erased in the above-described normal manner a certain voltage is applied to the control gate electrode 114 of the cell for a certain time. As a result of that, in case the memory cell is "over erased", charge carriers enter into the floating gate 112 of the memory cell while, in case the memory cell requires more time to reach the erased state, holes enter into the floating gate 112. According to the method, the threshold voltage of the memory cell can be fixed at a predetermined value.
However, the above three methods have the following problems. In the method using the erase verify reference circuit, a device using the memory cell is complex and disadvantaged in integration and manufacturing cost.
In the method for lowering the concentration of phosphorus in the floating gate 112, the extent of charge by F-N tunneling due to an error in coupling rate and the insulating silicon oxide layer 108 can not be decreased.
In the method using hot holes, the hot holes deteriorate the insulating silicon oxide layer 108. Furthermore, dissipation power is necessary to generate the hot holes.